Integrated semiconductor circuits may be supplied to the electronic equipment manufacturer in the form of a small "chip" of rectangular shape, more specifically referred to as a "die", for bonding into a suitable package that is then mounted in a circuit board. The die is the end result of a fabrication process, "processing", which, as viewed from a macroscopic level, begins with a wafer of high purity semiconductor material, the "substrate", typically a grown single crystal silicon from which the wafer was sliced, with the wafer being of a size sufficient to support a number of copies of an integrated circuit to be processed simultaneously.
For example, an upper surface area defined by a wafer of four inches in diameter and a thickness of 50 mils represents one standard wafer size in present commercial practice. Many Integrated Circuits fit within that space. Through a series of processing steps, which are known, involving oxidizing, masking, which may be of the photolithographic stencil like technique or of the more modern laser or electron beam pattern formation apparatus, etching, metallizing, impurity doping and deposition a pattern of a large number of semiconductor devices are formed on the wafer's surface. Typically the semiconductors are arranged in discrete groups about the surface of the wafer with the groups spaced from one another by border strips, an effective "no man's land" between the groups. The semiconductors within the group are sometimes referred to as "cells". And each group of cells, referred to as an integrated circuit or simply IC, is of a generally rectangular shape and essentially forms an integrated circuit that provides a function specified by the circuit designer. This overall function may be a "calculator chip" that functions as the circuit for a calculator, a "computer chip" that functions as the element of a computer, or a "display chip" that serves as the electronic circuit to process signals for a visual display as example.
By such fabrication technique, many copies of a desired electronic circuit represented in the group of cells constituting an integrated circuit are reproduced simultaneously in a single processing of one wafer, providing obvious production advantage. As one of the final steps in the fabrication process the wafer is subsequently "diced" or, as otherwise stated, "sliced", using a saw, into frangible rectangular shaped sections and broken apart, effectively cutting the wafer into prescribed corresponding rectangular segments or dies, each of which contains an integrated circuit. Each IC chip from the wafer is a monolithic integrated circuit that is intended to perform the predetermined electronic functions specified by the circuit designer as in the examples earlier stated when the chip is installed in a circuit board or other electronic apparatus.
An individual integrated circuit, referred to in the preceding paragraphs as a collective group of cells, as viewed on a more microscopic level, contains very large numbers of semiconductor devices, referred to as transistors, interconnected by electrical wiring as achieves predefined electronic functions that collectively attain the overall function that the IC is intended to achieve. The IC is said to be formed of "cells", transistors of one form or another, arranged in an electronic circuit. The simplest form of cell may be referred to as a "gate". In turn the gate typically includes four transistors arranged in two pairs which are electrically isolated from the next cell. At a more elemental level, the gate may consist of only two transistors when the conventional "sea of gates" approach is used in which electrical isolation is achieved by having an associated pair of transistors wired to the electrically non-conducting or "off" state permanently.
Of those cells there are two major classes, used in what is usually called application specific integrated circuits, "ASIC", that are commonly used to allow circuit designers to place large numbers of logic circuits on a single or common large scale or very large scale, collectively "LSI", integrated chip. One of these classes or types of cells is known as a standard cell, wherein each logical function is implemented as a custom designed circuit which can then be placed anywhere on the chip and be wired to other functions, circuits or cells. This provides a real convenience as the designer does not need to develop all the cells needed for the IC design. In this standard cell approach, the sizes of the devices or transistors and the layout of the circuits are optimized for each logical function so that density and performance characteristics are nearly comparable to a custom designed chip.
In the standard cell type of IC all steps in the fabrication of the wafer or chip are "personalized" for each particular design. Thus if any significant changes are to be made to the design, an entirely new mask must be made for every step in the fabrication process and the fabrication must again begin from a bare semiconductor wafer.
In contrast to the standard cell, gate array cells, typically referred to as "macros" are not personalized until the fabrication process reaches the first contact level to the conductive material which interconnects the devices or transistors in the gate array. That is, a typical gate array chip is formed by making rows of P-channel and N-channel transistors, if complementary metal oxide semiconductor, "CMOS", technology is used, arranged in functionally generic cells on the surface of the chip. For each discrete logic function available in the library of macros, a "personality" of conductors is defined in a known manner which interconnects the devices or transistors located within one or more cells to perform a desired electronic function, such as inverting or latching. Fundamental logic circuits, the "macros", such as an invertor, AND, OR, NAND or NOR gates are formed with MOS FET's in one or in several adjacent basic generic cells. Any logical function implemented on the gate array chip uses the same set of "background" transistors or devices and, if any changes are to be made in the circuit, only the last few steps, the conductor and contact steps, in the fabrication process need to be altered.
This wafer processing technique is often referred to as the "master slice" technique, wherein a semiconductor wafer that is to contain many integrated circuits, as earlier described, is processed up to a defined step in manufacture and then is placed on hold in inventory as a "master slice" for later completion. The present invention redefines specific aspects of the master slice technique and creates a new form of master slice semiconductor wafer.
Of the different type of gate arrays available, the complementary metal oxide semiconductor, "CMOS", gate array is most widely used for LSI semiconductor devices. Heat created through power dissipation of the transistor poses a limitation in the quantities of transistors that may be packed onto a single substrate. CMOS transistors have the advantage of lower-power operation than other types and, therefore permits a higher degree of integration of the LSI semiconductor devices. The present invention also takes advantage of CMOS technology.
In this well known gate array or master slice semiconductor device, many basic elements thus are formed in a semiconductor chip prior to determining the function to be performed by the chip. Each basic element set is fabricated with typical transistors, resistors, and so on to form a basic circuit, referred to as a basic cell. Up to this point, the master slice semiconductor device is mass produced in large quantities. When a specific circuit function is subsequently identified, interconnecting lines are formed between the basic cells and in each basic cell using a specified mask to obtain an LSI semiconductor device containing the desired functional circuits.
Much like the modern housing developer acquires a large plot of land and partially builds a large quantity of houses of identical construction very rapidly at one time to achieve maximum construction efficiency and lesser cost and then "banks" or leaves the partially complete houses undone in inventory for later completion by subsequent installation of the floor coverings, wall coverings and window coverings after the specific home buyers needs are identified; whereby carpets or floor tiles, drapes or window blinds, tailored to the individual's wishes, are selected and installed, completing and effectively "customizing" the individual house in the group, so too the manufacturer of integrated circuit configurable gate arrays or other elemental transistor arrays for like reasons, but with greater complexity, also partially builds and banks in its inventory partially completed integrated circuit chips on wafers whose final construction and function, the "personalization" or "customization" of the pre-formed gate array, awaits identification of the chip buyers specific needs, whence final design and processing are undertaken and completed.
And like the developer subdivides the land into preformed plots on which the buyer has no say, incidental to the sale of homes in the development, so too the semiconductor manufacturer assembles many gate arrays on a single wafer and then subdivides the wafer as individual "chips" or "dies" by slicing the wafer into many separate rectangular shaped parts.
By using the master slice gate array approach, both initial IC designs and later modifications to those designs can be obtained more quickly and cheaply than in a standard cell design or custom design, though with some impact to chip performance and density when compared to the standard cell and/ or custom design chip. The technique enables significant reductions in both design and manufacturing time since one need only design and fabricate the specified masks when manufacturing a new semiconductor device
Furthermore, since a large number of basic cells are regularly arranged in both the column and row directions on the semiconductor substrate and form a standardized matrix pattern in a master slice semiconductor device, it is very easy to employ computer aided automatic wiring to form the electrical interconnections.
Gate arrays are manufactured in fixed or standard sizes at present, approximately twenty to thirty different sizes. Each size requires an inventory of fixed size base arrays, made up of generic gates, or cells. An inventory of each size is maintained in the hope that most, if not all, of the IC designs that are presented to the fabricator will fit onto one of the various sizes of gate arrays in that inventory. As presently practiced in the industry, software routines perform essentially all of the macro placement and conductor routing for the given personalization. Such "place and route" procedure represents a significant cost in the procurement of a "personalized" gate array IC chip.
Often personalizations do not quite fit a particular master slice size. Consequently the personalization must be placed on the next larger size master slice. To do so often entails additional wire routing design expense. Further the number of personalizations available from the master slice will be less than is the case in which the master slice size fortuitously exactly fits the given design. By providing a master slice that is completely uncommitted to any particular die size, obvious economies are achieved. The present invention produces a configurable gate array wafer that eliminates the need for stockkeeping of different size master slice gate arrays.
A single integrated circuit die may next be considered in more detail as further background to the invention. The known gate array devices have a cell layout in which a plurality of basic cells are arrayed in rows and columns in the central portion and a plurality of input and output cells disposed in the peripheral portion surrounding the array. More specifically, each of the basic cells in one type of CMOS configurable gate arrays includes typically two N channel MOS FET's and typically two P channel MOS FET's. The N channel MOS FET's in each basic cell have an arrangement of a drain region, a gate, a source region, a second gate and a second drain region in the stated order in parallel with the row direction. The P channel MOS FETS in each cell are disposed at a portion adjacent to the corresponding N channel MOS FET's in the column direction and, similarly to the N channel MOS FET's have a drain region, a gate, a source, a second gate and a second drain region in the stated order in parallel with the row direction. The P channel MOS FETs in other basic cells in the same row are disposed side by side. The N and P channel MOS FETS are wired with the first layer wiring disposed over the N and P channel MOS FETS and second layer wiring disposed over the first layer wiring In another conventional gate array, referred to as the "sea of gates", the MOS FET transistors have source drain regions, which are shared by the adjoining FETs. Although the transistors are not segregated into electrically isolated groups of four in the sea of gates structure and are in a continuum, a grouping of three pairs or six transistors in such an array may be regarded as a cell for purposes of explanation.
Reference to gate arrays and to prior literature concerning gate arrays is presented in the patents to Fitzgerald U.S. Pat. No. 4,742,383, Takayama U.S. Pat. No. 4,701,777, and Usui U.S. Pat. No. 4,771,327; and related information is presented in Percival U.S. Pat. No. 4,691,434, Schallenberger U.S. Pat. No. 4,766,476, Rowson U.S. Pat. No. 4,745,084, Varshney U.S. Pat. No. 4,703,436, Heath U.S. Pat. No. 4,688,072 and Furtek U.S. Pat. No. 4,700,187 and may serve as background for the interested reader.
Of particular note U.S. Pat. No. 4,733,288 granted Mar. 22, 1988 to Sato for a Gate Array Chip also illustrates a row and column arrangement of the gates in the configurable gate array. Moreover Sato recognizes a limitation in the existing master slice structure, noting that quite often an individual gate array contains many more gates than are needed in a given application; and since the surplus gates are unavailable to adjoining chips on the wafer, such surplus gates are effectively wasted due to the lack of necessary input and output type semiconductors. As noted by Sato, a conventional gate array LSI chip does not have any region for forming an input output "pad" in the internal area; and that it is thus not possible according to Sato to cut the integrated circuit gate array chip into a plurality of smaller sized chips. To salvage these otherwise wasted cells for other application, which by themselves can form an independent IC, Sato proposes a design change that allows a standard chip to be modified and cut up into smaller parts, smaller dies, by cutting away some portions unneeded; much akin to saving "string" or a "waste not, want not" approach. To do so Sato requires that extra input output transistors be added to the extended gate array, such added transistors being different in structure from those transistors in the gate array used for logic functions, reasoning:
"The gate width of a transistor in an input buffer circuit, however, is narrower than the gate width of a transistor in the basic cell arrays, with the result that an input buffer circuit cannot be formed by the basic cells. To make it possible to form an input buffer circuit and a protective circuit, a bulk pattern, comprising an impurity diffusion region is formed under the surface of the wiring region between the basic cell row. The input output circuit region, in which the bulk pattern is formed, is adapted to be a source region or a drain region of a MOS semiconductor transistor or a base or emitter of a bipolar transistor in an input buffer circuit or a diffusion region of a protective diode in a protective circuit."
The Sato patent thus describes a technique to make the gate array chip using the master slice technique more versatile by slicing a given chip into several parts; slicing along paths between rows and columns of the basic cells, while leaving enough space between the cut border and the adjacent peripheral edge of the row or column of cells to allow for insertion or formation of additional transistor input output circuits distinct from the transistors in the cells that the Sato gate array arrangement requires. With a saw that is thin enough so as not to extend across bordering rows (or columns) of gates, estimated as being spaced by about 10 mils on the horizontal direction and 8 mils along the vertical direction, the chip may be sliced between the adjacent rows, leaving enough room in the border area to form the additional circuits to serve the input output function. Essentially by adding more transistor devices the new structure proposed by Sato reforms a conventional gate array of smaller size from one of larger size, with the gates surrounded by input output buffers of transistor construction different than the transistors forming the gates.
The present invention likewise provides a configurable gate array of greater versatility. The configurable gate array invention disclosed herein also requires input/output buffers as was the case in the Sato patent and the prior art. A decided advantage to the invention, however, is that the addition of diffusion regions in between rows of cells as found necessary to provide the input output buffers in the Sato gate array structure is not required.
Further, in the disclosed invention the input/output transistors are not required to be placed along the periphery of the gate array; they may be physically located anywhere in the array. In the invention the transistors used to provide that function are one and the same as other transistors in the array; the transistor types are not different. As a result the circuit design is made more efficient; the circuit designer no longer is bound to use only a specific group of transistors as the input/output function which restricted the wiring paths.
Conventional technological wisdom as evidenced in the cited patent literature and in the applicant's prior experience was that the layout of elemental cells was made in an array of rectangular geometry with a group of the cells, a row and column of cells, sufficient in number to form the customer identified integrated circuit complete with bonding pads and input/output circuits surrounding the macro cells, and to form as many such groups on and distributed over the available wafer surface with sufficient spacing or boundary between each array, spacing identified by the incorporation of straight "scribe lines" or saw lanes formed on the wafer surface, allowing the wafer to later be "diced" to remove the individual chips, the "dies"; as accomplished by slicing the wafer along those scribe lines.
In this conventional wafer processing technique the scribe lines were formed on the wafer either prior to or concurrently with the formation of the plurality of arrays as choice incidental to the layout of the several integrated circuits on the wafer, since adequate spacing between the many gate arrays on the wafer was provided to allow for slicing in the prior process. The lines were visible to the operator. The operator could thus align the saw to the position of dividing space, set the equipment and allow it to slice automatically, without requiring the addition of a paint or other marker in the channel, but which could be added to enhance the scribe line as desired.
The present invention also uses saw lanes or scribe lines to like advantage. A characteristic distinguishing the invention from such prior fabrication process is that scribe lines are made only after formation of the transistor cells on the wafer; more specifically, scribe lines are formed over and extend across rows and/or columns of transistors that were formed on the wafer in the preliminary wafer processing steps. The present invention effectively does not incorporate border areas at the gate level, the areas between individual gates or cells being effectively borderless in the sense of the prior devices. The borders are formed only during the process of personalizing the gate array. By analogy to the home developer as above, it would be like the home developer personalizing the house further, beyond carpets and drapes, by allowing the buyer to add rooms and special gardens, which takes up more land, as an added feature to some of the homes; only thereafter dividing the land on which the homes sit into odd shaped lots, instead of regular shaped lots, according to the need after the final shape of the home and gardens is finally determined.
As those skilled in the art quickly surmise from the foregoing statements regarding the scribe lines, the present invention also incorporates a slicing step, one which illustrates a further characteristic to the invention; slicing the wafer along the afore described scribe lines, and completely destroying, if not obliterating, the rows and/or columns of elemental transistor gate cells underlying the slicing path, which are expended thusly in attaining the benefit which the disclosed invention provides. In contrast to prior teachings, such as presented in the Sato patent, a benefit of the invention comes from destroying individual gate cells, not by saving unused ones.
By spreading transistor gates over the entire wafer surface any configuration of a gate array, typically arranged in a rectangular pattern, may be "mapped" or fitted onto a single wafer in multiple copies, eliminating the need for different wafers with different standard size gate arrays. By employing arrangements of some of those same transistors as input and output circuits, to be formed during the personalization of the integrated circuit formed from the array, no additional special transistor fabrication is needed for those functions.
In as much as the greatest hurdle to introduction of new integrated circuit designs is to surmount the "up front" set up and design costs, the present invention makes new designs easier and quick; hence reduces the cost of introducing new integrated circuit designs and allows for more rapid introduction of new chips of benefit to the user.
In accordance with the foregoing, an object of the invention is to provide a configurable gate array that is of more versatile application in the formation of integrated circuits; to realize a configurable gate array that is adaptive to integrated circuits of many sizes; a nearly continuous spectrum of sizes.
Another object of the invention is to provide a master slice gate array wafer or master slice which eliminates the need for pre-formed boundaries between the individual transistor cells in the array and thereby supports fabrication of all sizes of ASIC chips; a gate array master slice which is considered variable in size, essentially providing a "one size, fits all" configurable gate array which permits greater efficiency in the production of semiconductor integrated circuits;
Still another object of the invention is to provide a new process for fabricating ASIC chips of any size that requires only a single size of configurable gate array as an essential starting ingredient, and to provide lower cost of low volume ASIC chip requirements and quicker turn around time in designing and fabricating ASIC chips;
An additional object of the invention to lower the cost of design and production of new integrated circuit designs while maintaining the quality of the circuits produced; to allow production of logic products of optimal density and enhance the ability to implement rapid turn around time for design changes in and for new designs of such logic products;
A still further object of the invention is to eliminate the necessity of maintaining an inventory of different sized configurable gate array chips, thereby reducing manufacturing and stocking expense and permitting manufacturing quality to be enhanced by limiting the size of arrays to be manufactured to a single size;
An ancillary object to the invention is to release "place and route" software from the heretofore existing constraints of chip size boundary conditions and allow development of new more efficient software such as the place and route function which could be designed and operated more quickly than heretofore possible; and
An ancillary object to the invention is to provide reinforcement structure to minimize crystal fracture during sawing of a semiconductor wafer as increases yields of functional chips and/or permit increased packing of transistors on the wafer for increased density.